{"id":9997,"date":"2026-08-22T01:06:10","date_gmt":"2026-08-21T19:36:10","guid":{"rendered":"https:\/\/internshala.com\/competitions\/?p=9997"},"modified":"2026-08-22T01:06:11","modified_gmt":"2026-08-21T19:36:11","slug":"vlsid-2027-tape-out-contest","status":"publish","type":"post","link":"https:\/\/internshala.com\/competitions\/vlsid-2027-tape-out-contest\/","title":{"rendered":"VLSID 2027 Tape-Out Contest"},"content":{"rendered":"\n<h2 class=\"wp-block-heading\">\ud83d\udccc<strong>About the Event<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">The VLSID 2027 Tape-Out Contest is a national-level integrated circuit design competition aimed at recognising innovative silicon tape-out projects developed by students at academic institutions in India. Conducted as part of the 40th International Conference on VLSI Design and the 26th International Conference on Embedded Systems, the contest allows students who completed a Digital or Analog tape-out during 2025 or 2026 to showcase their work before the semiconductor and VLSI community.<\/p>\n\n\n\n<hr class=\"wp-block-separator has-text-color has-alpha-channel-opacity has-background is-style-default\" style=\"background-color:#f0f0f0;color:#f0f0f0\"\/>\n\n\n\n<h2 class=\"wp-block-heading\">\u2139\ufe0f <strong>Event Details<\/strong><\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Event Type: <\/strong>VLSI \/ Semiconductor Design \/ Integrated Circuit Design Contest<\/li>\n\n\n\n<li><strong>Mode of Conduct: <\/strong>Hybrid process<\/li>\n\n\n\n<li>Initial entries are submitted online.<\/li>\n\n\n\n<li>Shortlisted participants are invited to attend VLSID 2027 in Bengaluru.<\/li>\n\n\n\n<li><strong>Contest Categories:<\/strong><\/li>\n\n\n\n<li><strong>Digital Tape-Out: <\/strong>Designs implemented using digital logic.<\/li>\n\n\n\n<li><strong>Analog Tape-Out: <\/strong>Analog, mixed-signal or RF circuit designs.<\/li>\n\n\n\n<li><strong>Conference Dates: <\/strong>January 2\u20136, 2027<\/li>\n\n\n\n<li><strong>Venue:<\/strong> Sheraton Grand Whitefield, Bengaluru, Karnataka, India.<\/li>\n\n\n\n<li><strong>Conference: <\/strong>40th International Conference on VLSI Design &amp; 26th International Conference on Embedded Systems.<\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-text-color has-alpha-channel-opacity has-background is-style-default\" style=\"background-color:#f0f0f0;color:#f0f0f0\"\/>\n\n\n\n<h2 class=\"wp-block-heading\">\ud83d\udcc5 <strong>Important Dates<\/strong><\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Submission Deadline: <\/strong>September 30, 2026<\/li>\n\n\n\n<li><strong>Notification of Finalists: <\/strong>November 10, 2026<\/li>\n\n\n\n<li><strong>Final Slides\/Poster Submission:<\/strong> December 10, 2026<\/li>\n\n\n\n<li><strong>VLSID 2027 Conference:<\/strong> January 2\u20136, 2027<\/li>\n\n\n\n<li><strong>Conference Venue: <\/strong>Sheraton Grand Whitefield, Bengaluru.<\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-text-color has-alpha-channel-opacity has-background is-style-default\" style=\"background-color:#f0f0f0;color:#f0f0f0\"\/>\n\n\n\n<h2 class=\"wp-block-heading\">\ud83c\udfaf <strong>Eligibility &amp; Rules<\/strong><\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Eligibilty:<\/strong><\/li>\n\n\n\n<li>The tape-out must be associated with an academic institution in India.<\/li>\n\n\n\n<li>Students who have completed a Digital or Analog tape-out during 2025 or 2026 are eligible to participate.<\/li>\n\n\n\n<li>Entries must fall under either:<\/li>\n\n\n\n<li>Digital Tape-Out<\/li>\n\n\n\n<li>Analog Tape-Out, including analog, mixed-signal or RF designs.<\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-text-color has-alpha-channel-opacity has-background is-style-default\" style=\"background-color:#f0f0f0;color:#f0f0f0\"\/>\n\n\n\n<h2 class=\"wp-block-heading\">\ud83c\udfc6 <strong>Benefits for the Participants<\/strong><\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li>5 Digital Tape-Out entries will be selected as finalists.<\/li>\n\n\n\n<li>5 Analog Tape-Out entries will be selected as finalists.<\/li>\n\n\n\n<li>All shortlisted entries will be invited to attend VLSID 2027.<\/li>\n\n\n\n<li>Shortlisted participants will be felicitated at VLSID 2027, giving their work visibility at one of India&#8217;s major semiconductor and VLSI conferences.<\/li>\n\n\n\n<li>Participants get an opportunity to showcase their silicon-design work to a conference attended by researchers, engineers, academics and semiconductor-industry professionals.<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n","protected":false},"excerpt":{"rendered":"<p>\ud83d\udcccAbout the Event The VLSID 2027 Tape-Out Contest is a national-level integrated circuit design competition aimed at recognising innovative silicon tape-out projects developed by students at academic institutions in India.<\/p>\n","protected":false},"author":10,"featured_media":9999,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[2],"tags":[],"class_list":["post-9997","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-contests"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.9 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>VLSID 2027 Tape-Out Contest<\/title>\n<meta name=\"description\" content=\"Apply for the VLSID 2027 Tape-Out Contest for Digital and Analog IC designs. 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