We are looking for candidates that have done prior projects using SystemVerilog and Verilog. If you do not have this background, do not apply. The candidate should have worked on generating test vectors and creating power management code, for both verification and implementation. They should have knowledge of UPF and CPF.
Selected intern's day-to-day responsibilities include:
1. Developing a system model of a sensor-based SoC
2. Defining the power domains
3. Generating the CPF files for this model
Only those candidates can apply who:
1. are available for full time (in-office) internship
2. can start the internship between 17th Jun'19 and 17th Jul'19
3. are available for duration of 3 months
4. have relevant skills and interests
Job offer: On successful conversion to a permanent employee, the candidate can expect a salary of Rs. 400000 to 500000 /year
Mirabilis Design Incorporation is a software company providing simulation solutions for the design of electronics and semiconductor products. Our customers range from AMD and IBM to GoPro and Toyota. VisualSim (our product) is used to create a prototype of a future electronics product and identify system problems. The solutions save the companies considered in their production schedule and improve the quality of the final product.
