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VHDL/Verilog/FPGA Engineering Internship

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VHDL/Verilog/FPGA Engineering

UnivLabs

Visakhapatnam, Gurgaon

Start Date

Starts immediatelyImmediately

Duration

6 Months

Stipend

₹ 15,000-25,000 /month

APPLY BY

30 Oct' 19

145 applicants

About the internship

Selected intern's day-to-day responsibilities include:

1. Writing RTL level code in an HDL language for Xilinx
2. Work using FPGA architecture
3. Work using Xilinx platform

Skill(s) required

Verilog VHDL

Earn certifications in these skills

Learn Arduino

Learn VLSI Design

Learn React

Learn Git & Github

Learn Deep Learning

Learn Data Structures & Algorithms

Learn SAS Programming

Learn AR/VR

Who can apply

Only those candidates can apply who:

1. are available for full time (in-office) internship

2. can start the internship between 16th Oct'19 and 15th Nov'19

3. are available for duration of 6 months

4. have relevant skills and interests

* Women wanting to start/restart their career can also apply.

Perks

Certificate Letter of recommendation Flexible work hours Informal dress code 5 days a week Job offer

Additional information

Job offer: On successful conversion to a permanent employee, the candidate can expect a salary of Rs. 600000 to 1100000 /year

Number of openings

About UnivLabs

Website

UnivLabs is one of the world's leading medical technology companies, which is driven to make healthcare better. We offer state-of-the-art electronic endoscope medical equipment which is reliable as well as affordable. Our devices and tools enable medical professionals around the world to deliver a better therapeutic outcome. At UnivLabs, we strive to be the most valuable partner to experts and customers with high aspirations through the timely provision of appropriate solutions that meet their high-level needs.

Activity on Internshala

Hiring since July 2016

110 opportunities posted

36 candidates hired