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VHDL/Verilog/FPGA Engineering Internship in Visakhapatnam, Gurgaon at UnivLabs

VHDL/Verilog/FPGA Engineering

UnivLabs

Visakhapatnam, Gurgaon

Start Date Duration Stipend Posted On Apply By
Immediately
6 Months ₹15000-25000 /Month 16 Oct'19 30 Oct'19
Full time
With job offer
 
About UnivLabs (http://www.univlabs.in):
UnivLabs is one of the world's leading medical technology companies and, together with our customers, is driven to make healthcare better.

We offer state of the art electronic endoscope medical equipment which is reliable as well as affordable. Our devices and tools enable medical professionals around the world to deliver a better therapeutic outcome. At UnivLabs, we strive to be the most valuable partner to experts and customers with high aspirations through the timely provision of appropriate solutions that meet their high-level needs.
About the Internship:
Selected intern's day-to-day responsibilities include:

1. Writing RTL level code in an HDL language for Xilinx
2. Work using FPGA architecture
3. Work using Xilinx platform
# of Internships available: 2
Skill(s) required: Verilog and VHDL
Who can apply:
Only those candidates can apply who:
  1. are available for full time (in-office) internship
  2. can start the internship between 16th Oct'19 and 15th Nov'19
  3. are available for duration of 6 months
  4. have relevant skills and interests
** Women willing to start/restart their career can also apply.
Perks:
Certificate, Letter of recommendation, Job offer (On successful conversion to a permanent employee, the candidate can expect a salary of Rs. 6 to 11 Lac/annum), Informal dress code.

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