VHDL/Verilog/FPGA Engineering Internship in Visakhapatnam, Gurgaon at UnivLabs
VHDL/Verilog/FPGA Engineering
Start Date
Starts immediatelyImmediately
Duration
6 Months
Stipend
10000-15000 /month
Apply By
19 Jun' 20
Internship with job offer
Internship with job offer
About UnivLabs
UnivLabs is one of the world's leading medical technology company, which is driven to make healthcare better. We offer state of the art electronic endoscope medical equipment which is reliable as well as affordable. Our devices and tools enable medical professionals around the world to deliver a better therapeutic outcome. At UnivLabs, we strive to be the most valuable partner to experts and customers with high aspirations through the timely provision of appropriate solutions that meet their high-level needs.
About the internship
Selected intern's day-to-day responsibilities include:

1. Writing RTL level code in an HDL language for Xilinx
2. Work using FPGA architecture
3. Work using Xilinx platform
4.Integration of IP
Skill(s) required
Verilog VHDL FPGA Synthesis and Prototyping
Who can apply

Only those candidates can apply who:

1. are available for full time (in-office) internship

2. can start the internship between 22nd May'20 and 26th Jun'20

3. are available for duration of 6 months

4. have relevant skills and interests

* Women willing to start/restart their career can also apply.

Perks
Certificate Letter of recommendation Flexible work hours 5 days a week Job offer
Additional Information

Job offer: On successful conversion to a permanent employee, the candidate can expect a salary of Rs. 6 to 11 Lac/annum

Number of openings
2

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