VHDL/Verilog/RTL/Xilinx FPGA Engineering Intern

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VHDL/Verilog/RTL/Xilinx FPGA Engineering

UnivLabs

Start Date
Starts immediatelyImmediately
Duration
6 Months
Stipend
₹ 15,000-20,000 /month
APPLY BY
3 Dec' 20
Posted 3 weeks ago
Internship with job offer

About the internship

Selected intern's day-to-day responsibilities include:

1. Write RTL level code in an HDL language for Xilinx
2. Work using FPGA architecture
3. Work using the Xilinx platform
4. Work on integration of IP

Skill(s) required

FPGA Synthesis and Prototyping Verilog VHDL

Who can apply

Only those candidates can apply who:

1. are available for full time (in-office) internship

2. can start the internship between 18th Nov'20 and 23rd Dec'20

3. are available for duration of 6 months

4. have relevant skills and interests

* Women wanting to start/restart their career can also apply.

Added requirements

1. Candidates who have executed the project on FPGA and have at least one year of exposure to FPGA during their coursework

Perks

Certificate Letter of recommendation Flexible work hours 5 days a week Job offer
Additional information

Job offer: On successful conversion to a permanent employee, the candidate can expect a salary of Rs. 800000 to 1100000 /year

Number of openings

2

About UnivLabs

UnivLabs is one of the world's leading medical technology companies, which is driven to make healthcare better. We offer state-of-the-art electronic endoscope medical equipment which is reliable as well as affordable. Our devices and tools enable medical professionals around the world to deliver a better therapeutic outcome. At UnivLabs, we strive to be the most valuable partner to experts and customers with high aspirations through the timely provision of appropriate solutions that meet their high-level needs.
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