VHDL/Verilog/RTL/XILINX FPGAEngineering Internship in Gurgaon at UnivLabs
Applications are closed for this internship. Click here to browse more internships.
VHDL/Verilog/RTL/XILINX FPGAEngineering
Start Date
Starts immediatelyImmediately
Duration
6 Months
Stipend
15000-20000 /month
Apply By
6 Aug' 20
54 applicants
Internship with job offer
Internship with job offer
54 applicants
About UnivLabs
UnivLabs is one of the world's leading medical technology company, which is driven to make healthcare better. We offer state of the art electronic endoscope medical equipment which is reliable as well as affordable. Our devices and tools enable medical professionals around the world to deliver a better therapeutic outcome. At UnivLabs, we strive to be the most valuable partner to experts and customers with high aspirations through the timely provision of appropriate solutions that meet their high-level needs.
About the internship
Selected intern's day-to-day responsibilities include:

1. Write RTL level code in an HDL language for Xilinx
2. Work using FPGA architecture
3. Work using Xilinx platform
4. Work on integration of IP
Skill(s) required
Verilog VHDL FPGA Synthesis and Prototyping
Who can apply

Only those candidates can apply who:

1. are available for full time (in-office) internship

2. can start the internship between 8th Jul'20 and 12th Aug'20

3. are available for duration of 6 months

4. have relevant skills and interests

* Women wanting to start/restart their career can also apply.

Perks
Certificate Letter of recommendation 5 days a week Job offer
Additional Information

Job offer: On successful conversion to a permanent employee, the candidate can expect a salary of Rs. 8 to 11 Lac/annum

Number of openings
2

Save yourself from fraud!

If an employer asks you to pay any security deposit, registration fee, laptop fee, etc., do not pay and notify us immediately. Remember, Internshala doesn't charge a fee from the students to apply to a job or an internship & we don't allow other companies to do so either.