Hands on experience in custom memory and/or memory compiler design techniques and architectural tradeoffs like single versus dual rail, high density versus high performance, Vmin, performance, read/write assists etc.
Ability to contribute technically as well as lead a team.
Institute memory IP QA (quality assurance) audits/checks to ensure high quality IP deliveries.
Strong familiarity with memory characterization and EDA view generation (timing, noise, power, Mbist etc.) process.