Design and develop PLLs for Automotive and SERDES applications.
Experience in designing LC Tank and ring oscillator based designs.
Experience in designing complex architectures like ADPLL, MPLL, HSPLL etc.,
Meet critical specifications and design targets for skew, jitter, lock up, stability etc.,
Able to guide junior engineers and execute as a team
1. Candidates with minimum 7 years of experience.
Annual CTC: ₹ 25,00,000 - 30,00,000 /year
Information above is Internshala's interpretation and paraphrasing of what we found on the shared link.