Senior Design Verification Engineer Job

Senior Design Verification Engineer

Bangalore

Start date
Starts Immediately
CTC (ANNUAL)
₹ 3,00,000 - 8,00,000 ₹ 3,00,000 - 8,00,000 /year
Experience
4-6 years
4-6 years experience
Apply By
11 May' 24
Posted 1 week ago
Job

About the job

Senior RTL Verification Lead / RTL Verification Engineer

Are you an experienced RTL Verification professional looking for your next challenge? Look no further!

Qualifications:

BE/ME/MTech/MS in Electrical Engineering
6 to 12 years of RTL verification experience for the Senior RTL Verification Lead position
4 to 5 years of relevant industry experience for the RTL Verification Engineer position
Proficiency in advanced verification methodologies like UVM/OVM/VMM/System Verilog
Experience in constrained random stimulus generation, assertion-based verification, and functional coverage techniques.
Knowledge of register verification standards, NLP/GLS verification flows
Strong experience in IP level and sub-system level verification on protocols such as PCI-E, UCIe, HBM, etc.
Relevant experience in enabling and verifying controller interoperability testing at the sub-system level is a plus

Responsibilities:
Lead a highly motivated verification team responsible for DV for IPs like UCIe, HBM, PCIe, Bus logic etc. (Senior RTL Verification Lead)
Implement advanced verification methodologies such as UVM/OVM/VMM/System Verilog
Generate constrained random stimulus and perform assertion-based verification.
Ensure functional coverage techniques are applied effectively.
Apply register verification standards and NLP/GLS verification flows.
Conduct IP level and sub-system level verification on protocols like PCI-E, UCIe, HBM, etc.
Enable and verify controller interoperability testing at the sub-system level.

Experience:
6 to 12 years of RTL verification experience for the Senior RTL Verification Lead position
1 to 3 years of relevant industry experience for the RTL Verification Engineer position

If you meet the qualifications and are ready to make a difference, apply now! Send your resume to
poojakarve@arf-design.com

#RTLVerification #SeniorRTLVerificationLead #ASICDesign #VerificationMethodologies #PCIe #UCIe #HBM #JobOpportunity #HiringNow #JoinOurTeam

Who can apply

1. Candidates with minimum 4 years of experience.

Salary

Annual CTC: ₹ 3,00,000 - 8,00,000 /year

Editor’s note
Information above is Internshala's interpretation and paraphrasing of what we found on the shared link.
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