Senior Design Verification Engineer Job

Job Responsibilities
Proficient in Verilog, System Verilog, UVM, object-oriented programming,
Firm understanding of constrained random functional verification, coverage, and assertions.
Experience with test plan development and development of verification environments from ground up.
Experience with verification of complex blocks, regressions and coverage closure.
Experience with gate level simulations and debug.
Excellent debugging, analytical and problem-solving skills.
Strong inter-personal, teamwork and communication skills.
Expected to be highly independent, proactive and result-oriented to achieve verification goals.

Preferred Qualifications:
Knowledge of I2C, UART, SPI, Ethernet, Video (DisplayPort, CSI/DSI), PCIe and Audio I2S interfaces.
Experience with lab silicon bring-up, validation and production test support.

Information above is Internshala's interpretation and paraphrasing of what we found on the shared link.